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(R)
X5323, X5325
(Replaces X25323, X25325)
Data Sheet October 27, 2005 FN8131.1
CPU Supervisor with 32Kb SPI EEPROM
FEATURES * Selectable watchdog timer * Low VCC detection and reset assertion --Five standard reset threshold voltages --Re-program low VCC reset threshold voltage using special programming sequence --Reset signal valid to VCC = 1V * Determine watchdog or low voltage reset with a volatile flag bit * Long battery life with low power consumption --<50A max standby current, watchdog on --<1A max standby current, watchdog off --<400A max active current during read * 32Kbits of EEPROM * Built-in inadvertent write protection --Power-up/power-down protection circuitry --Protect 0, 1/4, 1/2 or all of EEPROM array with Block LockTM protection --In circuit programmable ROM mode * 2MHz SPI interface modes (0,0 & 1,1) * Minimize EEPROM programming time --32-byte page write mode --Self-timed write cycle --5ms write cycle time (typical) * 2.7V to 5.5V and 4.5V to 5.5V power supply operation * Available packages --14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP * Pb-free plus anneal available (RoHS compliant) BLOCK DIAGRAM
Watchdog Transition Detector WP SI SO SCK CS/WDI Data Register Command Decode & Control Logic VCC Threshold Reset Logic Protect Logic
DESCRIPTION These devices combine four popular functions, Power-on Reset Control, Watchdog Timer, Supply Voltage Supervision, and Block Lock Protect Serial EEPROM Memory in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. Applying power to the device activates the power-on reset circuit which holds RESET/RESET active for a period of time. This allows the power supply and oscillator to stabilize before the processor can execute code. The Watchdog Timer provides an independent protection mechanism for microcontrollers. When the microcontroller fails to restart a timer within a selectable time out interval, the device activates the RESET/RESET signal. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The device's low VCC detection circuitry protects the user's system from low voltage conditions, resetting the system when VCC falls below the minimum VCC trip point. RESET/RESET is asserted until VCC returns to proper operating level and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil's unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the threshold for applications requiring higher precision.
Watchdog Timer Reset
RESET/RESET Status Register 8Kbits 8Kbits 16Kbits EEPROM Array Reset & Watchdog Timebase X5323 = RESET X5325 = RESET
VCC VTRIP
+ -
Power-on and Low Voltage Reset Generation
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X5323, X5325 Ordering Information
PART NUMBER RESET (ACTIVE LOW) X5323P-4.5A X5323PZ-4.5A (Note) X5323PI-4.5A PART MARKING X5323P AL PART NUMBER RESET (ACTIVE HIGH) X5325P-4.5A PART MARKNIG X5325P AL X5325P Z AL X5325P AM X5325P Z AM X5325 AL VCC RANGE TEMP (V) VTRIP RANGE RANGE (C) 4.5-5.5 4.5-4.75 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 X5325V Z AL 0 to 70 -40 to 85 X5325V Z AM X5325P X5325P Z X5325P I X5325P Z I X5325 X5325 Z X5325 I X5325 Z I 4.5-5.5 4.25-4.5 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 X5325V Z 0 to 70 -40 to 85 X5325V Z I X5325P AN X5325P Z AN X5325P AP X5325P Z AP X5325 AN 2.7-5.5 2.85-3.0 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 PACKAGE 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free)
X5323P Z AL X5325PZ-4.5A X5323P AM X5325PI-4.5A
X5323PIZ-4.5A (Note) X5323P Z AM X5325PIZ-4.5A X5323S8-4.5A X5323 AL X5325S8-4.5A
X5323S8Z-4.5A (Note) X5323 Z AL X5323S8I-4.5A* X5323S8IZ-4.5A* (Note) X5323V14-4.5A X5323V14Z-4.5A (Note) X5323V14I-4.5A X5323V14IZ-4.5A (Note) X5323P X5323PZ (Note) X5323PI X5323PIZ (Note) X5323S8* X5323S8Z* (Note) X5323S8I* X5323S8IZ* (Note) X5323V14* X5323V14Z* (Note) X5323V14I* X5323V14IZ* (Note) X5323P-2.7A X5323PZ-2.7A (Note) X5323PI-2.7A X5323V Z I X5323P AN X5323 AM X5323 Z AM
X5325S8Z-4.5A (Note) X5325 Z AL X5325S8I-4.5A X5325S8IZ-4.5A (Note) X5325V14-4.5A X5325 AM X5325 Z AM
X5323V Z AL X5325V14Z-4.5A (Note) X5325V14I-4.5A X5323V Z AM X5325V14IZ-4.5A (Note) X5323P X5323P Z X5323P I X5323P Z I X5323 X5323 Z X5323 I X5323 Z I X5323V X5323V Z X5325P X5325PZ X5325PI X5325PIZ X5325S8* X5325S8Z* (Note) X5325S8I* X5325S8IZ* (Note) X5325V14* X5325V14Z* (Note) X5325V14I* X5325V14IZ* (Note) X5325P-2.7A
X5323P Z AN X5325PZ-2.7A X5323P AP X5325PI-2.7A
X5323PIZ-2.7A (Note) X5323P Z AP X5325PIZ-2.7A X5323S8-2.7A* X5323S8Z-2.7A* (Note) X5323S8I-2.7A* X5323S8IZ-2.7A* (Note) X5323 AN X5323 Z AN X5323 AP X5323 Z AP X5325S8-2.7A
X5325S8Z-2.7A (Note) X5325 Z AN X5325S8I-2.7A X5325S8IZ-2.7A (Note) X5325 AP X5325 Z AP
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X5323, X5325 Ordering Information (Continued)
PART NUMBER RESET (ACTIVE LOW) X5323V14-2.7A X5323V14Z-2.7A (Note) X5323V14I-2.7A X5323V14IZ-2.7A (Note) X5323P-2.7 X5323PZ-2.7 (Note) X5323PI-2.7 X5323PIZ-2.7 (Note) X5323S8-2.7* PART MARKING X5323V AN PART NUMBER RESET (ACTIVE HIGH) X5325V14-2.7A X5325V Z AN PART MARKNIG VCC RANGE TEMP (V) VTRIP RANGE RANGE (C) 2.7-5.5 2.85-3.0 0 to 70 0 to 70 -40 to 85 X5325V Z AP X5325P F X5325P Z F X5325P G X5325P Z G X5325 F 2.7-5.5 2.55-2.7 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 -40 to 85 0 to 70 0 to 70 -40 to 85 X5325V Z G -40 to 85 PACKAGE 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld PDIP 8 Ld PDIP (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 8 Ld SOIC 8 Ld SOIC (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free) 14 Ld TSSOP 14 Ld TSSOP (Pb-free)
X5323V Z AN X5325V14Z-2.7A (Note) X5325V14I-2.7A X5323V Z AP X5325V14IZ-2.7A (Note) X5323P F X5323P Z F X5323P G X5323P Z G X5323 F X5325P-2.7 X5325PZ-2.7 X5325PI-2.7 X5325PIZ-2.7 X5325S8-2.7*
X5323S8Z-2.7* (Note) X5323 Z F X5323S8I-2.7* X5323 G
X5325S8Z-2.7* (Note) X5325 Z F X5325S8I-2.7* X5325 G
X5323S8IZ-2.7* (Note) X5323 Z G X5323V14-2.7* X5323V14Z-2.7* (Note) X5323V14I-2.7* X5323V14IZ-2.7* (Note) X5323V Z G X5323V Z F
X5325S8IZ-2.7* (Note) X5325 Z G X5325V14-2.7* X5325V14Z-2.7* (Note) X5325V14I-2.7* X5325V14IZ-2.7* (Note) X5325V F X5325V Z F
*Add "-T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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PIN CONFIGURATION
14 Ld TSSOP 8 Ld SOIC/PDIP CS/WDT SO WP VSS 1 2 3 4 X5323/25 8 7 6 5 VCC RESET/RESET SCK SI CS/WDT SO NC NC NC WP VSS 1 2 3 4 5 6 7 X5323/25 14 13 12 11 10 9 8 VCC RESET/RESET NC NC NC SCK SI
PIN DESCRIPTION Pin (SOIC/PDIP)
1
Pin TSSOP
1
Name
CS/WDI
Function
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW transition on CS is required. Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The absence of a HIGH to LOW transition within the watchdog time out period results in RESET/RESET going active. Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the serial clock (SCK) clocks the data out. Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first. Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO pin. Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to "lock" the setting of the watchdog timer control and the memory write protect bits. Ground Supply Voltage Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-up at about 1V and remains active for 200ms after the power supply stabilizes. No internal connections
2 5
2 8
SO SI
6
9
SCK
3 4 8 7
6 7 14 13
WP VSS VCC RESET/ RESET
3-5,10-12
NC
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PRINCIPLES OF OPERATION Power-on Reset Application of power to the X5323/X5325 activates a power-on reset circuit. This circuit goes active at about 1V and pulls the RESET/RESET pin active. This signal prevents the system microprocessor from starting to operate with insufficient voltage or prior to stabilization of the oscillator. As long as RESET/RESET pin is active, the device will not respond to any Read/Write instruction. When VCC exceeds the device VTRIP value for 200ms (nominal) the circuit releases RESET/RESET, allowing the processor to begin executing code. Low Voltage Monitoring During operation, the X5323/X5325 monitors the VCC level and asserts RESET/RESET if supply voltage falls below a preset minimum VTRIP. The RESET/RESET signal prevents the microprocessor from operating in a power fail or brownout condition. The RESET/RESET signal remains active until the voltage drops below 1V. It also remains active until VCC returns and exceeds VTRIP for 200ms. Watchdog Timer The watchdog timer circuit monitors the microprocessor activity by monitoring the WDI input. The microprocessor must toggle the CS/WDI pin periodically to prevent a RESET/RESET signal. The CS/WDI pin must be toggled from HIGH to LOW prior to the expiration of the watchdog time out period. The state of two nonvolatile control bits in the status register determine the watchdog timer period. The microprocessor can change these watchdog bits, or they may be "locked" by tying the WP pin LOW and setting the WPEN bit HIGH. VCC Threshold Reset Procedure The X5323/X5325 has a standard VCC threshold (VTRIP) voltage. This value will not change over normal operating and storage conditions. However, in applications where the standard VTRIP is not exactly right, or for higher precision in the VTRIP value, the X5323/X5325 threshold may be adjusted. Setting the VTRIP Voltage This procedure sets the VTRIP to a higher voltage value. For example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V, this procedure directly makes the change. If the new setting is lower than the current setting, then it is necessary to reset the trip point before setting the new value.
SCK
To set the new VTRIP voltage, apply the desired VTRIP threshold to the Vcc pin and tie the CS/WDI pin and the WP pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to both SCK and SI and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 1. Set VTRIP Voltage
CS VP SCK VP SI
Resetting the VTRIP Voltage This procedure sets the VTRIP to a "native" voltage level. For example, if the current VTRIP is 4.4V and the VTRIP is reset, the new VTRIP is something less than 1.7V. This procedure must be used to set the voltage to a lower value. To reset the VTRIP voltage, apply a voltage between 2.7 and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the SCK pin HIGH. RESET/RESET and SO pins are left unconnected. Then apply the programming voltage VP to the SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP and the sequence is complete. Figure 2. Reset VTRIP Voltage
CS VCC
VP SI
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Figure 3. VTRIP Programming Sequence Flow Chart
VTRIP Programming
Execute Reset VTRIP Sequence
Set VCC = VCC Applied = Desired VTRIP
New VCC Applied = Old VCC Applied + Error
Execute Set VTRIP Sequence
New VCC Applied = Old VCC Applied - Error
Apply 5V to VCC
Execute Reset VTRIP Sequence
Decrement VCC (VCC = VCC - 10mV)
NO
RESET pin goes active?
YES Error Emax Error Emax
Measured VTRIP Desired VTRIP Error < Emax
Emax = Maximum Desired Error
DONE
Figure 4. Sample VTRIP Reset Circuit
VP 4.7K NC VTRIP Adj. Program + 1 8 2 7 X5323/25 3 6 4 5 NC NC 4.7K RESET
10K
10K
Reset VTRIP Test VTRIP Set VTRIP
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SPI SERIAL MEMORY The memory portion of the device is a CMOS serial EEPROM array with Intersil's block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil's proprietary Direct WriteTM cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. It contains an 8-bit instruction register that is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Table 1. Instruction Set Instruction Name
WREN SFLB WRDI/RFLB RSDR WRSR READ WRITE
Note:
Write Enable Latch The device contains a write enable latch. This latch must be SET before a write operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid write cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows: 7
WPEN
6
FLB
5
4
3
BL1
2
BL0
1
WEL
0
WIP
WD1 WD0
The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a "1", a nonvolatile write operation is in progress. When set to a "0", no write is in progress.
Instruction Format*
0000 0110 0000 0000 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010 Set flag bit
Operation
Set the write enable latch (enable write operations) Reset the write enable latch/reset flag bit Read status register Write status register (watchdog, block lock, WPEN & flag bits) Read data from memory array beginning at selected address Write data to memory array beginning at selected address
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix WREN CMD WEL
0 1 1 1
Status Register WPEN
X 1 0 X
Device Pin WP#
X 0 X 1
Block Protected Block
Protected Protected Protected Protected
Block Unprotected Block
Protected Writable Writable Writable
Status Register WPEN, BL0, BL1 WD0, WD1
Protected Protected Writable Writable
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The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. Status Register Bits BL1
0 0 1 1
The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. Status Register Bits WD1
0 0 1 1
WD0
0 1 0 1
Watchdog Time Out (Typical)
1.4 seconds 600 milliseconds 200 milliseconds disabled (factory default)
Array Addresses Protected X5323/X5325
None (factory default) $0C00-$0FFF $0800-$0FFF $0000-$0FFF
BL0
0 1 0 1
The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The flag bit is automatically reset upon power-up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure.
Notes: 1. The Watch Dog Timer is shipped disabled. (WD1 = 1, WD0 = 1) 2. The factory default for Memory Block Protection is `None'. (BL1 = 0, BL0 = 0)
Figure 5. Read EEPROM Array Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25
26 27 28 29 30
Instruction SI
16 Bit Address 15 14 13 3 2 1 0
Data Out High Impedance SO 7 MSB 6 5 4 3 2 1 0
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In Circuit Programmable ROM Mode This mechanism protects the block lock and watchdog bits from inadvertent corruption.
In the locked state (programmable ROM mode) the WP pin is LOW and the nonvolatile bit WPEN is "1". This mode disables nonvolatile writes to the device's status register.
Write Sequence Prior to any attempt to write data into the device, the "Write Enable" Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW, then the WREN instruction is clocked into the device. After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the write operation without taking CS HIGH after issuing the WREN instruction, the write operation will be ignored. To write data to the EEPROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be "0's". The WRITE operation minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock continues, the counter will roll back to the first address of the page and overwrite any data that may have been previously written. For the page write operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4). To write to the status register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0 and 1 must be "0". While the write is in progress following a status register or EEPROM Sequence, the status register may be read to check the WIP bit. During this time the WIP bit will be high. OPERATIONAL NOTES The device powers-up in the following state: - The device is in the low power standby state. - A HIGH to LOW transition on CS is required to enter an active state and receive an instruction. - SO pin is high impedance. - The write enable latch is reset. - The flag bit is reset. - Reset signal is active for tPURST. Data Protection The following circuitry has been included to prevent inadvertent writes: - A WREN instruction must be issued to set the write enable latch. - CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.
Setting the WP pin LOW while WPEN is a "1" while an internal write cycle to the status register is in progress will not stop this write operation, but the operation disables subsequent write attempts to the status register. When WP is HIGH, all functions, including nonvolatile writes to the status register operate normally. Setting the WPEN bit in the status register to "0" blocks the WP pin function, allowing writes to the status register when WP is HIGH or LOW. Setting the WPEN bit to "1" while the WP pin is LOW activates the programmable ROM mode, thus requiring a change in the WP pin prior to subsequent status register changes. This allows manufacturing to install the device in a system with WP pin grounded and still be able to program the status register. Manufacturing can then load configuration data, manufacturing time and other parameters into the EEPROM, then set the portion of memory to be protected by setting the block lock bits, and finally set the "OTP mode" by setting the WPEN bit. Data changes now require a hardware change. Read Sequence When reading from the EEPROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address are sent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. The read operation is terminated by taking CS high. Refer to the read EEPROM Array Sequence (Figure 1). To read the status register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruction. After the RDSR opcode is sent, the contents of the status register are shifted out on the SO line. Refer to the read status register sequence (Figure 2).
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Figure 6. Read Status Register Sequence
CS
0 SCK
1
2
3
4
5
6
7
8
9
10
11 12 13 14
Instruction SI
Data Out SO High Impedance 7 MSB 6 5 4 3 2 1 0
Figure 7. Write Enable Latch Sequence
CS 0 SCK 1 2 3 4 5 6 7
SI
SO
High Impedance
Figure 8. Write Sequence
CS 0 SCK Instruction SI 16 Bit Address 15 14 13 3 2 1 0 7 6 5 4 Data Byte 1 3 2 1 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 5 Data Byte 3 4 3 2 1 0 6 5 Data Byte N 4 3 2 1 0
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Figure 9. Status Register Write Sequence
CS 0 SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction SI 7 6 5 4
Data Byte 3 2 1 0
SO
High Impedance
SYMBOL TABLE
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
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ABSOLUTE MAXIMUM RATINGS Temperature under bias ................... -65C to +135C Storage temperature ........................ -65C to +150C Voltage on any pin with respect to VSS .... -1.0V to +7V D.C. output current ............................................... 5mA Lead temperature (soldering, 10s) .................... 300C COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0C -40C Max. 70C +85C Device Option -2.7 or -2.7A Blank or -4.5A Supply Voltage 2.7V to 5.5V 4.5V-5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Limits Symbol
ICC1 ICC2 ISB1 ISB2 ISB3 ILI ILO VIL
(1)
Parameter
VCC write current (active) VCC read current (active) VCC standby current WDT = OFF VCC standby current WDT = ON VCC standby current WDT = ON Input leakage current Output leakage current Input LOW voltage Input HIGH voltage Output LOW voltage Output LOW voltage Output LOW voltage Output HIGH voltage Output HIGH voltage Output HIGH voltage Reset output LOW voltage
Min.
Typ.
Max.
5 0.4 1 50 20
Unit
mA mA A A A A A V V V V V V V V
Test Conditions
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC = 5.5V CS = VCC, VIN = VSS or VCC, VCC =3.6V VIN = VSS to VCC VOUT = VSS to VCC
0.1 0.1 -0.5 VCC x 0.7
10 10 VCC x 0.3 VCC + 0.5 0.4 0.4 0.4
VIH(1) VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 VOLS
2V < VCC 3.3V, IOL = 1mA VCC 2V, IOL = 0.5mA VCC > 3.3V, IOH = -1.0mA VCC 2V, IOH = -0.25mA IOL = 1mA
VCC > 3.3V, IOL = 2.1mA
VCC - 0.8 VCC - 0.4 VCC - 0.2 0.4
2V < VCC 3.3V, IOH = -0.4mA
V
CAPACITANCE TA = +25C, f = 1MHz, VCC = 5V Symbol
COUT(2) CIN
(2)
Test
Output capacitance (SO, RESET/RESET) Input capacitance (SCK, SI, CS, WP)
Max.
8 6
Unit
pF pF
Conditions
VOUT = 0V VIN = 0V
Notes: (1) VIL min. and VIH max. are for reference only and are not tested. (2) This parameter is periodically sampled and not 100% tested.
12
FN8131.1 October 27, 2005
X5323, X5325
EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC
5V 5V 4.6k
A.C. TEST CONDITIONS
Input pulse levels Input rise and fall times Input and output timing level VCC x 0.1 to VCC x 0.9 10ns VCC x0.5
2.06k Output 3.03k 100pF RESET/RESET
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Serial Input Timing 2.7-5.5V Symbol
fSCK tCYC tLEAD tLAG tWH tWL tSU tH tRI(3) tFI(3) tCS tWC(4) Clock frequency Cycle time CS lead time CS lag time Clock HIGH time Clock LOW time Data setup time Data hold time Input rise time Input fall time CS deselect time Write cycle time 500 10
Parameter
Min.
0 500 250 250 200 250 50 50
Max.
2
Unit
MHz ns ns ns ns ns ns ns
100 100
ns ns ns ms
13
FN8131.1 October 27, 2005
X5323, X5325
Serial Input Timing
tCS CS tLEAD SCK tSU SI MSB IN tH tRI tFI LSB IN tLAG
SO
High Impedance
Serial Output Timing 2.7-5.5V Symbol
fSCK tDIS tV tHO tRO tFO
(3) (3)
Parameter
Clock frequency Output disable time Output valid from clock low Output hold time Output rise time Output fall time
Min.
0
Max.
2 250 250
Unit
MHz ns ns ns ns ns
0 100 100
Notes: (3) This parameter is periodically sampled and not 100% tested. (4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS tCYC SCK tV SO MSB Out MSB-1 Out tHO tWL LSB Out tDIS tWH tLAG
SI
ADDR LSB IN
14
FN8131.1 October 27, 2005
X5323, X5325
Power-Up and Power-Down Timing
VTRIP VCC 0 Volts tR RESET (X5323) tPURST tPURST tF tRPD VTRIP
RESET (X5323)
RESET Output Timing Symbol
VTRIP
Parameter
Reset trip point voltage, X5323-4.5A, X5323-4.5A Reset trip point voltage, X5323, X5325 Reset trip point voltage, X5323-2.7A, X5325-2.7A Reset trip point voltage, X5323-2.7, X5325-2.7 VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage) Power-up reset time out VCC detect to reset/output VCC fall time VCC rise time Reset valid VCC
Min.
4.5 4.25 2.85 2.55 100 100 100 1
Typ.
4.63 4.38 2.92 2.63 20 200
Max.
4.75 4.5 3.0 2.7 280 500
Unit
V
VTH tPURST tRPD tF tR
(5) (5) (5)
mV ms ns s s V
VRVALID
Note:
(5) This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI tCST RESET
tWDO
tRST
tWDO
tRST
RESET
15
FN8131.1 October 27, 2005
X5323, X5325
RESET/RESET Output Timing Symbol
tWDO
Parameter
Watchdog time out period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 0 CS pulse width to reset the watchdog Reset time out
Min.
100 450 1 400 100
Typ.
200 600 1.4 200
Max.
300 800 2 300
Unit
ms ms sec ns ms
tCST tRST
VTRIP Set Conditions
tTHD VCC VTRIP tTSU tVPS tP tVPH tRP
CS
tVPS VP
tVPH
tVPO
SCK VP SI tVPO
VTRIP Reset Conditions
VCC* tRP tVPS tP tVP1
CS
tVPS
tVPH
tVPO
SCK
VCC
VP SI
tVPO
*VCC > Programmed VTRIP
16
FN8131.1 October 27, 2005
X5323, X5325
VTRIP Programming Specifications VCC = 1.7-5.5V; Temperature = 0C to 70C Parameter
tVPS tVPH tP tTSU tTHD tWC tRP tVPO VP VTRAN Vta1 Vta2 Vtr Vtv
Description
SCK VTRIP program voltage setup time SCK VTRIP program voltage hold time VTRIP program pulse width VTRIP level setup time VTRIP level hold (stable) time VTRIP write cycle time VTRIP program cycle recovery period (between successive programming cycles) SCK VTRIP program voltage off time before next cycle Programming voltage VTRIP programed voltage range Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25C) Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25C) VTRIP program voltage repeatability (successive program operations) (programmed at 25C) VTRIP program variation after programming (0-75C). (programmed at 25C)
Min.
1 1 1 10 10
Max.
Unit
s s s s ms
10 10 0 15 1.7 -0.1 -25 -25 -25 18 5.0 +0.4 +25 +25 +25
ms ms ms V V V mV mV mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
17
FN8131.1 October 27, 2005
X5323, X5325
TYPICAL PERFORMANCE
VCC Supply Current vs. Temperature (ISB)
18 16 14 Reset (seconds) 12 Isb (A) 10 8 6 4 2 0 -40 25 Temp (C) 90 Watchdog Timer Off (VCC= 3V, 5V) Watchdog Timer On (VCC = 5V) Watchdog Timer On (VCC = 5V)
tWDO vs. Voltage/Temperature (WD1,0 = 1, 1)
1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 1.7 2.4 3.1 3.8 Voltage 4.5 5.2 90C 25C -40C
VTRIP vs. Temperature (programmed at 25C)
5.025 5.000 4.975 3.525 Voltage 3.500 3.475 2.525 2.500 2.475 0 25 Temperature 85 VTRIP = 2.5V VTRIP = 3.5V VTRIP = 5V
tWDO vs. Voltage/Temperature (WD1, 0 = 1, 0)
0.8 0.75 Reset (seconds) 0.7 0.65 0.6 0.55 0.5 0.45 1.7 2.4 3.1 3.8 Voltage 4.5 5.2 90C 25C -40C
tPURST vs. Temperature
205 200 195
tWDO vs. Voltage/Temperature (WD1, 0 0 = 0, 1)
205 200 195 Reset (seconds) 190 185 180 175 170 165 160 1.7 2.4 3.1 3.8 4.5 5.2 90C 25C -40C
190 Time (ms) 185 180 175 170 165 160 -40 25 Degrees C 90
Voltage
18
FN8131.1 October 27, 2005
X5323, X5325
PACKAGING INFORMATION 8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80) 0.158 (4.00) 0.244 (6.20) Pin 1 Index Pin 1
0.014 (0.35) 0.019 (0.49) 0.188 (4.78) 0.197 (5.00) (4X) 7
0.053 (1.35) 0.069 (1.75) 0.004 (0.19) 0.010 (0.25)
0.050 (1.27)
0.010 (0.25) X 45 0.020 (0.50)
0.050"Typical
0 - 8 0.0075 (0.19) 0.010 (0.25) 0.016 (0.410) 0.037 (0.937) 0.250"
0.050" Typical
FOOTPRINT
0.030" Typical 8 Places
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
19
FN8131.1 October 27, 2005
X5323, X5325
PACKAGING INFORMATION 8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92) 0.360 (9.14)
0.260 (6.60) 0.240 (6.10) Pin 1 Index Pin 1 0.300 (7.62) Ref. 0.060 (1.52) 0.020 (0.51)
Half Shoulder Width On All End Pins Optional Seating Plane 0.150 (3.81) 0.125 (3.18)
0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) 0.065 (1.65) 0.045 (1.14) 0.020 (0.51) 0.016 (0.41)
0.110 (2.79) 0.090 (2.29)
.073 (1.84) Max.
0.325 (8.25) 0.300 (7.62)
Typ. 0.010 (0.25)
0 15
NOTE: 1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
20
FN8131.1 October 27, 2005
X5323, X5325
PACKAGING INFORMATION 14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.193 (4.9) .200 (5.1)
.047 (1.20) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 21
FN8131.1 October 27, 2005

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